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general description the max2986 powerline transceiver utilizes state-of-the- art cmos design techniques to deliver the highest level of performance and flexibility. this highly integrated design combines the media access control layer (mac) and the physical layer (phy) in a single chip. the max2986 digital baseband and its companion device, the max2980* analog front-end (afe), offer a complete high-speed powerline communication solution that is fully compatible with third-party homeplug 1.0 devices. the max2986 digital transceiver utilizes maxim? advanced ofdm powerline engine with adaptive data rates up to 14mbps. the max2986? open architecture allows extensive programmability, feature enhancement capability, and improved testability in the mac for opti- mum performance. hence, this device is aimed at appli- cations such as local area networks (lans), audio, voice, home automation, industrial automation, and broadband-over-powerline (bpl), as well as spectral shaping and tone notching capability, providing an unparalleled level of flexibility to conform to the disparate local regulatory bodies. maxim? modified ofdm tech- nique allows shaping of power spectral density of the transmitted signal arbitrarily to accommodate any desired subcarrier set and to place spectral nulls at any unwanted frequency location. the automatic channel adaptation and interference rejection features of the max2986 guarantee outstanding performance. privacy is provided by a 56-bit des encryption with key manage- ment. the max2986 operates with ieee 802.03 standard media independent interface (mii), reduced media inde- pendent interface (rmii), buffered fifo data communica- tion, ieee 802.03 compatible 10/100 ethernet mac, or usb 1.1 interfaces. these interfaces allow the max2986 to be paired with almost any data communication devices to use in a variety of information appliances. applications features ? single-chip powerline networking transceiver ? up to 14mbps data rate ? 4.49mhz to 20.7mhz frequency band ? upgradeable/programmable mac spectral shaping including bandwidth and notching capability programmable preamble access to application protocol interface (api) 128kb internal sram ? jtag interface ? large bridge table: up to 512 addresses ? 56-bit des encryption with key management for secure communication ? advanced narrowband interference rejection circuitry ? ofdm-based phy 84 carriers automatic channel adaptation fec (forward error correction) dqpsk, dbpsk, robo ? on-chip interfaces 10/100 ethernet usb 1.1 mii/rmii/fifo ? compatible with homeplug 1.0 standard max2986 integrated powerline digital transceiver ________________________________________________________________ maxim integrated products 1 ordering information 19-3484; rev 0; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration and typical application circuit appear at end of data sheet. part temp range pin-package MAX2986CXV 0? to +70? 144 csbga homeplug is a registered trademark of homeplug powerline alliance, inc. * future product?ontact factory for availability. broadband-over-powerline local area networks (lans) multimedia-over-powerline voice-over-powerline industrial automation (remote monitoring and control) home automation security and safety
max2986 integrated powerline digital transceiver 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd33 = +3.3v, v dd18 = dv dd = av dd = +1.8v, av ss = dv ss = dgnd = 0, t a = 0? to +70?, unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd33 to dgnd .....................................................-0.5v to +4.6v v dd18 to dgnd, dv dd to dv ss ............................-0.5v to +2.5v av dd to av ss ........................................................-0.5v to +2.5v all other input pins...................................................-0.5v to +6v all other output pins.............................................-0.5v to +4.6v continuous power dissipation (t a = +70?) 144-bump csbga (derate 25.6mw/? at +70?) .........2045mw operating temperature range...............................0? to +70? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? parameter symbol conditions min typ max units power-supply characteristics digital-supply voltage range v dd33 guaranteed by psrr 3.0 3.3 3.6 v core-supply voltage range v dd18 1.62 1.8 1.98 v digital i/o supply current i dd33 41 ma core supply current i dd18 426 ma pll supply current i pll 8 ma output-voltage high v oh 2.3 v output-voltage low v ol 0.5 v logic input characteristics input high voltage v ih 2.0 5.5 v input low voltage v il -0.3 +0.8 v input leakage current i leak -80 +80 ? uarttxd, afefrz, afepdrx, aferen, afereset, afetxen, ethmdc, ethtxd[0], ethtxd[1], ethtxd[2], ethtxd[3], ethtxen, ethtxer, jrtck, miicrs, miirxdv, miirxer 4 afeclk 16 output high current i oh jtdo (tri-state port) 4 ma uarttxd, afefrz, afepdrx, aferen, afereset, afetxen, ethmdc, ethtxd[0], ethtxd[1], ethtxd[2], ethtxd[3], ethtxen, ethtxer, jrtck, miicrs, miirxdv, miirxer 4 afeclk 16 output low current i ol jtdo (tri-state port) 4 ma caution! esd sensitive device
max2986 integrated powerline digital transceiver _______________________________________________________________________________________ 3 pin description bump name function a1, l2 dv dd 1.8v p ll d i g i tal p ow er s up p l y. byp a ss to d v s s w i th a 10 0 nf cap aci tor as cl ose to the p i n as p ossi b l e. a2, l3 dv ss pll ground a3, m1 av dd 1.8v pll analog power supply. bypass to av ss with a 100nf capacitor as close to the pin as possible. a4 gpio[2] general-purpose input/output 2. gpio[2] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[2] if not used. the max2986 software uses gpio[2] to control external usb circuit. a5 gpio[22] general-purpose input/output 22. gpio[22] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[22] if not used. the max2986 mac uses gpio[22] for afe interface link status led (output) and boot pin bit 1 (input). a6, c1, c13, f12, j1, l1, l4, l10, m13 v dd33 3.3v digital power supply. bypass to dgnd with a 100nf capacitor as close to the pin as possible. a7 gpio[17] general-purpose input/output 17. gpio[17] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[17] if not used. a8 gpio[14] general-purpose input/output 14. gpio[14] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[14] if not used. a9 gpio[11] general-purpose input/output 11. gpio[11] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[11] if not used. the max2986 mac uses gpio[11] as processor id, bit 0 (input). a10 gpio[9] general-purpose input/output 9. gpio[9] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[9] if not used. the max2986 mac uses gpio[9] as serial data in nonvolatile memory interface. a11 gpio[7] general-purpose input/output 7. gpio[7] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[7] if not used. the max2986 mac uses gpio[7] as afe interface power- down signal. a12 gpio[5] general-purpose input/output 5. gpio[5] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[5] if not used. the max2986 mac uses gpio[5] as afe interface serial data signal. a13 gpio[4] general-purpose input/output 4. gpio[4] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[4] if not used. the max2986 mac uses gpio[4] for afe interface serial clock signal (output) and upper layer interface bit 0 (input). b1, c2, d4 d9, e3, e11, e12, e13, f4, f13, k5, k6, k8, k9, m10, m11, n1, n6 dgnd digital ground b2, m2 av ss analog pll ground b3 gpio[0] general-purpose input/output 0. gpio[0] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[0] if not used.
max2986 integrated powerline digital transceiver 4 _______________________________________________________________________________________ pin description (continued) bump name function b4 gpio[3] general-purpose input/output 3. gpio[3] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[3] if not used. b5 usbd+ usb interface data signal (+) b6 gpio[21] general-purpose input/output 21. gpio[21] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[21] if not used. the max2986 mac uses gpio[21] for afe interface collision led (output) and boot pin bit 0 (input). b7 gpio[18] general-purpose input/output 18. gpio[18] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[18] if not used. b8 gpio[15] general-purpose input/output 15. gpio[15] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[15] if not used. b9 gpio[12] general-purpose input/output 12. gpio[12] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[12] if not used. the max2986 mac uses gpio[12] as processor id, bit 1 (input). b10 gpio[10] general-purpose input/output 10. gpio[10] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[10] if not used. the max2986 mac uses gpio[10] as nonvolatile memory chip-select signal (output) and nonvolatile memory type, bit 1 (input). b11 gpio[8] general-purpose input/output 8. gpio[8] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[8] if not used. the max2986 mac uses gpio[8] as nonvolatile memory serial clock signal (output) and nonvolatile memory type, bit 0 (input). b12 gpio[6] general-purpose input/output 6. gpio[6] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[6] if not used. the max2986 mac uses gpio[6] as afe interface serial write signal (output) and upper layer interface bit 1 (input). b13, d1, d11, d12, d13, e1, k4, m12 n.c. no connection. must be left unconnected (floating output). c3 gpio[1] general-purpose input/output 1. gpio[1] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[1] if not used. c4 gpio[23] general-purpose input/output 23. gpio[23] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[23] if not used. the max2986 mac uses gpio[23] for afe interface link activity led (output) and boot pin bit 2 (input). c5 usbd- usb interface data signal (-) c6 gpio[20] general-purpose input/output 20. gpio[20] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[20] if not used. c7 gpio[19] general-purpose input/output 19. gpio[19] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[19] if not used. c8 gpio[16] general-purpose input/output 16. gpio[16] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[16] if not used. c9 gpio[13] general-purpose input/output 13. gpio[13] is in tri-state during boot up. connect a 100k ? pullup or pulldown resistor to gpio[13] if not used. the max2986 mac uses gpio[13] as processor id, bit 2 (input).
max2986 integrated powerline digital transceiver _______________________________________________________________________________________ 5 pin description (continued) bump name function c10, d10, e10, f10, g10, j10, k10 v dd18 +1.8v digital power supply. bypass to dgnd with a 100nf capacitor as close to the pin as possible. c11 jtms jtag test mode select c12 jtdi jtag test data input d2 usbreset active-low usb reset signal. connect to reset . d3 reset asynchronous, active-low reset input e2 jrtck jtag return test clock e4 afefrz analog front-end carrier sense indicator f1 afetxen analog front-end transmitter enable output f2 xin crystal input (30mhz) f3 xout crystal output f11 miitxen mii transmit enable g1 afereset afe reset g2 afedad[0] analog front-end dac/adc input/output 0 interface g3 afedad[1] analog front-end dac/adc input/output 1 interface g4 afedad[2] analog front-end dac/adc input/output 2 interface g11 jtdo jtag test data output g12 jtrst active-low jtag test reset g13 jtck jtag test clock h1 afedad[3] analog front-end dac/adc input/output 3 interface h2 afedad[4] analog front-end dac/adc input/output 4 interface h3 afedad[5] analog front-end dac/adc input/output 5 interface h4 afedad[6] analog front-end dac/adc input/output 6 interface h10 miirxdv mii receive data valid h11 bufrd active-low fifo read enable h12 bufcs active-low fifo chip enable h13 bufwr active-low fifo write enable j2 afedad[7] analog front-end dac/adc input/output 7 interface j3 afedad[8] analog front-end dac/adc input/output 8 interface j4 afedad[9] analog front-end dac/adc input/output 9 interface j11 miimdc mii management data clock j12 miidat[7] mii/fifo transmit/receive data [7] j13 miidat[5] mii/fifo transmit/receive data [5] k1 afeclk 50mhz afe clock k2 aferen analog front-end read enable output k3 afepdrx afe receiver power-down k7 uarttxd uart transmit k11 miicrs mii carrier sense k12 miidat[6] mii/fifo transmit/receive data [6]
max2986 integrated powerline digital transceiver 6 _______________________________________________________________________________________ pin description (continued) bump name function k13 miimdio mii management data l5 ethrxd[1] ethernet mii receive data bit 1 l6 uartrxd uart receive l7 ethtxd[3] ethernet mii transmit data bit 3 l8 ethtxd[2] ethernet mii transmit data bit 2 l9 ethtxclk ethernet mii transmit clock l11 miirxer mii receive-error indicator l12 miidat[4] mii/fifo transmit/receive data [4] l13 miidat[0] mii/fifo transmit/receive data [0] m3 ethmdc ethernet management data interface clock m4 ethrxclk ethernet mii receive clock m5 ethrxd[2] ethernet mii receive data bit 2 m6 ethrxd[0] ethernet mii receive data bit 0 m7 ethrxdv ethernet mii receive data valid m8 ethtxd[0] ethernet mii transmit data bit 0 m9 ethtxen ethernet mii transmit enable n2 ethcol ethernet mii collision n3 ethcrs ethernet mii carrier sense n4 ethmdio ethernet management data input/output n5 ethrxd[3] ethernet mii receive data bit 3 n7 ethrxer ethernet mii receive error n8 ethtxd[1] ethernet mii transmit data bit 1 n9 ethtxer ethernet mii transmit error n10 miiclk mii clock n11 miidat[3] mii/fifo transmit/receive data [3] n12 miidat[2] mii/fifo transmit/receive data [2] n13 miidat[1] mii/fifo transmit/receive data [1]
max2986 integrated powerline digital transceiver _______________________________________________________________________________________ 7 detailed description the max2986 powerline transceiver ic is a state-of-the- art cmos device, which delivers high performance at reduced cost. this highly integrated design combines the mac layer with the phy layer in a single chipset. the max2986 and the companion device, the max2980 afe, form a complete homeplug-compatible solution with a substantially reduced system cost. mii/rmii/fifo interface the mii/rmii/fifo block is the interface layer of the max2986 transceiver. this layer is designed to operate with ieee 802.3 standard mii, rmii, or any other devices using the fifo interface. the interface is a data channel that transfers data in packets, with flow controlled by the carrier sense (miicrs) signal. this signal controls the half-duplex transmission between the external host and the mac. while a frame reception is in progress, (miicrs and dsp engine afe register interface d-itcm on-chip ram controller encryption engine arm946 processor (mac software) i-cache d-cache dma engine address search engine timers ethernet mac interrupt controller gpio mii/rmii fifo controller on-chip rom afetxen afereset afedad0? afeclk aferen afepdrx afefrz usbd- usbd+ usbreset gpio0-23 miirxdv, miiclk miitxen, miimdc miicrs, miirxer miidat0-7, miimdio bufrd, bufcs bufwr ethcol, ethmdc, ethcrs, ethrxclk, ethmdio, ethrxd0-3, ethtxd0-3, ethrxdv, ethrxer, ethtxclk, ethtxen, ethtxer uartrxd uarttxd pll 1 pll 2 uart usb controller xin xout reset jtms, jtdo, jtdi jtrstn, jtck jtag i-itcm max2986 figure 1. max2986 functional diagram data external host max2986 mac/phy max2980 afe coupler powerline figure 2. powerline chipset system block diagram arm is a registered trademark of arm ltd.
max2986 integrated powerline digital transceiver 8 _______________________________________________________________________________________ table 1. upper layer interface-selection pin settings interface gpio[3] gpio[6] gpio[4] mii 0 0 1 rmii 0 1 0 fifo 0 1 1 miirxdv are high), the external host must wait until the completion of reception and the deassertion of miicrs before starting a transmission. when sending two con- secutive frames, the minimum time the external host needs to wait is the one-frame transfer time plus an interframe gap. note: for information such as signal timing characteris- tics and electrical characteristics, refer to the ieee 802.3u. note: the mii signals miicol and miitxer are not used, as the powerline networking device is able to detect and manage all transmission failures. the sig- nals miitxclk and miirxclk have the same source and are referred to as miiclk in this document. in mii mode, the data is transferred synchronously with a 2.5mhz/25mhz clock. data transmission in mii is in nibble format so the data transmission rate is 10mbps/100mbps. in rmii mode, the data is transferred synchronously with a 5mhz/50mhz clock. data transmission in mii is in 2-bit format so the data transmission rate is 10mbps/100mbps. in fifo mode, data is read and written in byte format on each positive edge of bufrd and bufwr. the only limitation in this mode is that bufrd and bufwr must be low for at least three pulses of miiclk to be consid- ered a valid signal. the upper layer interface can be selected according to the settings shown in table 1. mii interface signals table 2 describes the signals that provide data, status, and control to and from the max2986 in mii mode. table 2. mii signal description name lines i/o description miidat [3:0] 4i transmit data. data are transferred to the max2986 from the external mac across these four lines, one nibble at a time, synchronous to miiclk. miitxen 1i transmit enable. provides the framing for the ethernet packet from the ethernet mac. this signal indicates to the max2986 that valid data is present on miidat[3:0] and must be sampled using miiclk. miicrs 1 o carrier sense. logic-high indicates to the external host that traffic is present on the powerline and the host must wait until the signal goes invalid before sending additional data. when a packet is being transmitted, miicrs is held high. miidat [7:4] 4 o receive data. data are transferred from the max2986 to the external mac across these four lines, one nibble at a time, synchronous to miiclk. the max2986 properly formats the frame so the ethernet mac is presented with the expected preamble plus the start frame delimiter (sfd). miirxdv 1 o receive data valid. logic-high indicates that the incoming data on the miidat pins are valid. miirxer 1 o receive error. logic-high indicates to the external mac that the max2986 detected a decoding error in the receive stream. miiclk 1 i reference clock. a 2.5mhz (25mhz) clock in 10mbps (100mbps) as reference clock. management data unit miimdc 1 i management data clock. a 2.5mhz noncontinuous clock reference for the miimdio signal. miimdio 1 i/o management data input/output. a bidirectional signal that carries the data for the management data interface.
max2986 integrated powerline digital transceiver _______________________________________________________________________________________ 9 rxclk clock source (2.5mhz or 25mhz) txclk txen rxdv crs txd[3:0] rxd[3:0] rxer mdc mdio col gnd miitxen miiclk miirxdv miicrs miidat[3:0] miidat[7:4] miirxer miimdc miimdio bufwr bufrd bufcs v cc ethernet 802.3 mac (mii) mii interface mac max2986 phy figure 3. mac and phy connection in mii mode mii mac and phy connections figure 3 illustrates the connections between mac and phy in mii mode. although the tx and rx data paths are full duplex, the mii interface is operated in half- duplex mode. miirxdv is never asserted at the same time as miitxen. on transmit, the max2986 asserts miicrs some time after miitxen is asserted, and drops miicrs after miitxen is deasserted and when the max2986 is ready to receive another packet. when miicrs falls, the ethernet mac times out an interframe gap (ifg) (0.96? typ) and asserts miitxen again if there is another packet to send. this differs from the nominal behavior of miicrs in that miicrs can extend past the end of the packet by an arbitrary amount of time, while the max2986 is gaining access to the channel and transmitting the packet. macs in 10mbps mode do not use a jabber timeout, so there is no timing restriction on how long miicrs can assert (other than timeouts the max2986 may implement). transmissions are modulated onto the wire as soon as the transfer begins, as the mii fills the max2986 buffer faster than data needs to be made available to the modulator. when a packet arrives at the max2986, it attempts to gain access to the channel. this may not happen before the entire packet is transferred across the mii interface, so the max2986 buffers at least one ethernet packet to perform this rate adaptation. on receive, when the max2986 anticipates that it will have a packet demodulated, it raises miicrs to seize the half-duplex mii channel, waits a short time (an ifg), then possibly defers to miitxen (which may just have been asserted) plus an ifg, and then raises miirxdv to transfer the packet. at the end of the transfer, it drops miicrs unless the transmit buffer is full or there is another receive packet ready to transfer. this is illus- trated in figure 4, where one receive transfer is fol- lowed by a second, which defers to miitxen. data reception needs to have priority over transmission to ensure that the buffer empties faster than packets arrive off the wire. the longest the receiver needs to wait is the time to transfer one tx frame plus an ifg or approximately 134?. however, minimum size frames can arrive at a peak rate of one every 65?, so the receive-side buffer must accommodate multiple frames (but only a little more than one ethernet packet of data). miicrs miirxdv miitxen receive incoming ifg defer figure 4. receive defer in mii mode
max2986 integrated powerline digital transceiver 10 ______________________________________________________________________________________ mii signal timing?ransmitting when a frame in the external host is ready to transmit and miicrs is not high (the previous transmission has finished), the external host asserts miitxen, while data is ready on miidat[3:0]. in response, the max2986 asserts miicrs. while the external host keeps miitxen high, data is sampled synchronously with respect to miiclk into the max2986 through miidat. after transmission of the last byte of data and before the next positive edge of the miiclk, miitxen is reset by the external host. the transmission timing of the mii interface is illustrated in figure 5, with details in figure 6 and table 3. d ata data data data miicrs miidat miitxen miiclk figure 5. transmission behavior of the mii interface miidat miitxen miiclk t ih t is figure 6. mii interface?etailed transmit timing table 3. mii interface?etailed transmit timing* parameter description min units t is setup prior to positive edge of miiclk 2.5 ns t ih hold after positive edge of miiclk 2.5 ns * per ieee 802.3u standard.
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 11 miirxdv miidat miicrs miiclk d ata data data d ata data ifg miidat miirxdv miicrs miiclk t oh t ov figure 8. mii interface?etailed receive timing table 4. mii interface?etailed receive timing* parameter description max units t ov data valid after positive edge of miiclk 2.5 ns t oh nominal data hold time one miiclk period ns figure 7. receive behavior of the mii interface mii signal timing?eceiving when a frame is ready to send from the max2986 to the external host, the max2986 asserts miirxdv after ifg (which is about 0.96?), while there is no transmis- sion session in progress (with respect to miicrs). note: the receive process cannot start while a trans- mission is in progress. while the max2986 keeps miirxdv high, data is sam- pled synchronously with respect to miiclk from the max2986 through miidat. after the last byte of data is received, the max2986 resets miirxdv. receive timing of the mii interface is illustrated in figure 7, with details in figure 8 and table 4. * per ieee 802.3u standard.
max2986 integrated powerline digital transceiver 12 ______________________________________________________________________________________ reduced media independent interface (rmii) table 5 describes the signals that provide data, status, and control to the max2986 in rmii mode. in this mode, data is transmitted and received in bit pairs. the rmii mode connections are shown in figure 9. in case of an error in the received data, to eliminate the requirement for miirxer and still meet the requirement for undetected error rate, miidat[5:4] replaces the decoded data in the receive stream with 10 until the end of carrier activity. by this replacement, the crc check is guaranteed to detect an error and reject the packet. table 5. rmii signal description name data lines i/o description miidat[1:0] 2 i transmit data. data are transferred to the interface from the external mac across these two lines, one di-bit at a time. miidat[1:0] is 00 to indicate idle when miitxen is deasserted. miitxen 1 i transmit enable. this signal indicates to the max2986 that valid data is present on the miidat pins. miitxen is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented to the rmii. miidat[5:4] 2 o mii receive data. data is transferred from the max2986 to the external mac across these two lines, one di-bit at a time. upon assertion of miirxdv, the max2986 ensures that miidat[5:4] = 00 until proper receive decoding takes place. miirxdv 1 o receive data valid (crs_dv). when asserted high, miirxdv indicates that the incoming data on the miidat pins are valid. miiclk 1 i rmii reference clock. a continuous clock that provides the timing reference for miirxdv, miidat, miitxen, and miirxer. miiclk is sourced by the ethernet mac or an external source and its frequency is 5mhz (50mhz) in 10mbps (100mbps) data rate. management data unit miimdc 1 i mii management data clock. a 2.5mhz noncontinuous clock reference for the miimdio signal. miimdio 1 i/o mii management data input/output. it is a bidirectional signal that carries the data for the management data interface. refclk clock source (5mhz or 50mhz) txen crs_dv txd[1:0] rxd[1:0] mdc mdio miitxen miiclk miirxdv miidat[1:0] miidat[5:4] miimdc miimdio bufwr bufrd bufcs v cc ethernet 802.3 mac (rmii) rmii interface mac max2986 phy figure 9. mac-phy connection in rmii mode
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 13 rmii signal timing rmii transmit and receive timing are the same as for mii, except that the data are sent and received in 2-bit format and miicrs is removed. fifo interface signals table 6 describes signals that provide data, status, and control to and from the max2986 in buffering (fifo) mode. the fifo buffering interface is operated in half- duplex mode. miirxdv is never asserted at the same time as miitxen, but it is able to start transmission while receive is in progress. it is highly recommended to give reception a higher priority to avoid data loss. on transmit, the max2986 asserts miicrs after miitxen is asserted, and drops it after miitxen is deasserted and when the max2986 is ready to get another packet. when miicrs falls, it can be asserted again if there is another packet to send. transmissions are modulated onto the wire as soon as the transfer begins, as the interface fills the max2986 buffer faster than data needs to be made available to the modulator. when a packet arrives at the max2986, it attempts to gain access to the channel. since this may not happen before the entire packet is transferred across the interface, the max2986 buffers at least one ethernet packet to perform this rate adaptation. on receive; when the max2986 anticipates that it will have a packet demodulated, it raises miirxdv to iden- tify the upper layer that a packet is ready to transmit. miirxdv drops when the last byte is transmitted. receive direction transfers have priority over the transmit direction to ensure that the buffer empties faster than packets arrive. the minimum receive time is one tx frame plus an ifg. table 6. fifo signal description name data lines i/o description miidat[7:0] 8 i/o transmit/receive data. data are transferred to/from the max2986 from/to the external mac across this bidirectional port, one byte at a time. miitxen 1 i transmit enable [active high]. this signal indicates to the max2986 that the transmission has started, and that data on miidat should be sampled using bufwr . miitxen remains high to the end of the session. miicrs 1 o transmit in progress [active high]. when asserted high, miicrs indicates to the external host that outgoing traffic is present on the powerline and the host should wait until the signal goes low before sending additional data. bufwr 1i write [active low]. inputs a write signal to the max2986 from the external mac, writing the present data on miidat pins into the interface buffer on each positive edge. miirxdv 1 o receive data valid [active high]. when asserted high, miirxdv indicates that the incoming data on the miidat pins are valid. miirxer 1 o receive error [active high]. when asserted high, miirxer indicates to the external mac that an error has occurred during the frame reception. bufrd 1i read [active low]. inputs a read signal to the max2986 from the external mac, reading the data from the miidat pins of the max2986 on each positive edge. bufcs 1i chip select [active low]. when asserted low, it enables the chip. miiclk 1 i reference clock. used for sampling bufwr and bufrd .
max2986 integrated powerline digital transceiver 14 ______________________________________________________________________________________ fifo signal timing?ransmitting when the external host is ready to transmit a frame and miicrs is low (the previous transmission is finished), it asserts miitxen. the external host must assert miitxen if miirxdv is not high to avoid data loss. in response, miicrs is asserted by the max2986. while the external host keeps miitxen high, 1 byte of data is transmitted into the max2986 through miidat for each positive edge of bufwr . after transmission of the last byte of data, the external host resets miitxen. interactions between the external host and the max2986 baseband chip are shown in figure 10. the overall transmission timing of the fifo interface is illustrated in figure 11 with detailed timing shown in figure 12 and table 7. write to the fifo interface reset miitxen assert miitxen frame ava ilable? start counter = frame length yes no yes no crs or rxdv 0 1 figure 10. buffering transmission process from the external host view miicrs miidat miitxen bufwr d ata data data d ata data figure 11. transmission timing of the buffering (fifo) interface miidat miitxen t ih t is bufwr figure 12. fifo interface?etailed transmit timing table 7. fifo interface transmit timing* parameter description typ units t is setup prior to positive edge of bufwr 3ns t ih hold after positive edge of bufwr debounce** miiclk + 3 ns * per ieee 802.3u standard. ** the default value of the debounce parameter is 3.
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 15 fifo signal timing?eceiving when a frame is ready to send from the max2986 to the external host, the max2986 asserts miirxdv after an ifg (which is about 0.96?), while there is no trans- mission session in progress (with respect to miicrs). a receive process cannot start while a transmission is in progress. while the max2986 keeps miirxdv high, it sends 1 byte of data on miidat for each positive edge on bufrd . the first 2 bytes represent frame length in msb-first format. after the last byte of data is received, the max2986 resets miirxdv. the direction of bidirec- tional data pins is controlled through bufcs and bufrd pins. the max2986 enables data output drivers when bufcs = 0 and bufrd = 0. the interactions between the external host and the max2986 baseband is shown in figure 13 and the overall receive timing of the buffering interface is illustrated in figure 14, with details in figure 15 and table 8. read length (lsb) read from fifo interface read length (msb) miirxdv start counter = frame length yes no '1' '0' figure 13. buffering (fifo) interface receive process from the external host view d ata data d ata data frame length (msb) frame length (lsb) miirxdv miidat bufrd figure 14. receive timing of the buffering (fifo) interface t ov t oh bufrd miidat miirxdv miicrs figure 15. fifo interface?etailed receive timing table 8. fifo interfacereceive timing* parameter description min units t ov valid after negative edge of bufrd debounce** miiclk + 3 ns t oh hold after positive edge of bufrd 0ns * per ieee 802.3u standard. ** the default value of the debounce parameter is 3.
max2986 integrated powerline digital transceiver 16 ______________________________________________________________________________________ miimdc miimdio 32-bit optional preamble start write 5-bit physical address 5-bit register address ta from host 16-bit of d ata from host figure 16. write behavior of the management data unit miimdc miimdio 32-bit optional preamble start read 5-bit physical address 5-bit register address ta to host 16-bit of d ata from host figure 17. read behavior of the management data unit management data unit mdu the miimdio pin is a bidirectional data pin for the man- agement data interface. the miimdc signal is a clock reference for the miimdio signal. the write behavior of the management data unit is illustrated in figure 16. the read behavior of the management data unit is illus- trated in figure 17. ethernet interface the upper layer interface can be selected according to the pin settings shown in table 9. table 9. upper layer interface-selection pin settings interface gpio[3] gpio[6] gpio[4] mii 1 0 0 rmii 1 0 1
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 17 figure 18 shows the transmit timing. t txdv is the time that data must be valid for after a low-to-high transition on ethtxclk. t txdh is the time that data must be held after a low-to-high transition on ethtxclk. figure 19 shows the receive timing. t rxs is the setup time prior to the positive edge of ethrxclk. t rxh is the hold time after the positive edge of ethrxclk. for further infor- mation on the ethernet mac interface, refer to the ieee 802.3 specification. usb interface figure 20 shows the structure of a usb cable. the two pins usbd+ and usbd- are the data pins used in the usb interface, and correspond to d+ and d- in figure 20. v bus is nominally +5v at the source. figure 10 shows the upper layer interface pin setting to select usb. refer to the universal serial bus specification, revision 1.1 for more details on the usb interface. uart interface a serial asynchronous communication protocol using the uart standard interface is implemented in the max2986 baseband chip for the purpose of down- load/debugging mac software. to communicate with the current mac software, the uart interface must be configured as shown in table 11. to download and debug homeplug mac software, a null modem cable is required to make a serial connection as shown in figure 21. the max3221 is used as uart driver. table 10. upper layer interface-selection pin settings interface gpio[3] gpio[6] gpio[4] usb 0 0 0 table 11. uart interface configuration data rate 115,200bps data length 8 bits stop bit 1 bit flow control none ethtxclk ethtxen ethtxd[3:0] ethtxer t txdv t txdh t txdh > 5ns t txdv < 25ns figure 18. transmit timing for ethernet mac interface to the max2986 ethrxclk ethrxd[3:0], ethrxdv t rxs t rxh t rxh < 10ns t rxs > 10ns figure 19. receive timing for ethernet mac interface to the max2986 v bus d+ d- gnd v bus d+ d- gnd figure 20. usb cable uarttxd uartrxd baseband uart driver db9 connector max2986 max3221 in 1 6 2 7 3 8 4 9 5 out figure 21. max2986 uart interface with driver and db9 connector
max2986 integrated powerline digital transceiver 18 ______________________________________________________________________________________ applications information terminating interfaces to terminate either of the interfaces, the corresponding i/o pins should be configured as shown in tables 12?5. table 12. disabling usb interface location name direction terminate status c5 usbd- i/o connect to dgnd with a 5.1m ? resistor. b5 usbd+ i/o n.c. (no connection). table 13. disabling ethernet interface location name direction terminate status l9 ethtxclk i dgnd m4 ethrxclk i dgnd n2 ethcol i dgnd n3 ethcrs i dgnd m9 ethtxen o n.c. m7 ethrxdv i dgnd n9 ethtxer o n.c. n7 ethrxer i dgnd m6 ethrxd[0] i dgnd l5 ethrxd[1] i dgnd m5 ethrxd[2] i dgnd n5 ethrxd[3] i dgnd m8 ethtxd[0] o n.c. n8 ethtxd[1] o n.c. l8 ethtxd[2] o n.c. l7 ethtxd[3] o n.c. m3 ethmdc o n.c. n4 ethmdio i/o n.c.
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 19 interfacing the max2986 to the max2980 analog front end (afe) the interface to the max2980 afe chip uses a bidirec- tional bus to pass the digital data to and from the dac and adc. handshake lines help accomplish the data transfer as well as operation of the afe. figure 22 shows the interface signals. for afe pin configuration/ description, refer to the max2980 data sheet. table 15. disabling uart location name direction terminate status uarttxd k7 o n.c. uartrxd l6 i v dd table 14. disabling mii/rmii/fifo interface location name direction terminate status k11 miicrs o n.c. f11 miitxen i dgnd n10 miiclk i dgnd j12 miidat[7] i/o n.c. k12 miidat[6] i/o n.c. j13 miidat[5] i/o n.c. l12 miidat[4] i/o n.c. n11 miidat[3] i/o n.c. n12 miidat[2] i/o n.c. n13 miidat[1] i/o n.c. l13 miidat[0] i/o n.c. l11 miirxer o n.c. h10 miirxdv o n.c. h12 bufcs iv dd h11 bufrd iv dd h13 bufwr iv dd j11 miimdc i dgnd k13 miimdio i/o n.c. note: disabling the uart interface disables the mac code update and flash programming features of the chip. afedat[9:0] adc/dac afe max2980 baseband max2986 aferen enread afetxen entx afepdrx afefrz cs afeclk clk afereset gpio[7] si clock r/w serial data serial r/w select shdn gpio[4] sclk gpio[5] sdi/o gpio[6] swr resetin shrcrv figure 22. max2980 afe interface to the max2986
max2986 integrated powerline digital transceiver 20 ______________________________________________________________________________________ table 16. max2986 to afe signal interface description name data lines i/o description afetxen 1 o afe transmit enable. the afetxen signal is used to enable the transmitter of the afe. when afetxen and aferen are high, data is sent through the afedad[9:0] to the dac and then into the powerline. aferen 1 o setting bus direction. the aferen signal sets the direction of the data bus afedad[9:0]. when high, data can be sent from the max2986 to the dac in the afe, and when low, data is sent from the adc to the max2986. afepdrx 1 o afe receiver power-down. when the afe is in transmit mode, the afepdrx signal goes high, the receiver section of the afe is powered down. the max2980 features a transmit power-saving mode that reduces current dissipation. to use this power-saving mode, lower afepdrx prior to the end of a transmission. if this mode is not required, connect afepdrx to afetxen and aferen. afedad[9:0] 10 i/o afe 10-bit adc and dac bus. afedad[9:0] is the 10-bit bidirectional bus that connects the max2986 to the afe dac and adc. the direction of the bus is controlled by aferen described above. afefrz 1 o afe receive agc control. the afefrz signal controls the agc circuit in the receive path in the afe. when this signal is low, the gain circuit on the input signal continuously adapts for maximum sensitivity. this signal is raised high when the max2986 detects a valid preamble. after the afefrz signal is raised high, it continues to adapt for an additional short period of time, then it locks the currently adapted level on the incoming signal. the max2986 holds afefrz high while receiving a transmission, and then lowers for continuous adaptation for maximum sensitivity of other incoming signals. afeclk 1 o afe clock. a 50mhz clock generated for the max2980 afe. afereset 1 o a f e r e s e t . to p er for m a r eset on the m ax 2 980 afe , afe c lk m ust b e fr ee r unni ng and afe re s e t m ust b e lo w for typ i cal l y 1s. a r eset m ust b e p er for m ed at p ow er - up . gpio[6] 1 o afe serial interface read/write select. gpio[5] 1 i/o afe serial interface data (write/read). gpio[4] 1 o afe serial interface clock. gpio[7] 1 o afe power-down.
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 21 50mhz afe clk adc data output t daci t adco t clk = 20ns t adco = 2ns t daci = 3ns t clk dac data input figure 23. afe adc and dac timing diagram afe timing figure 23 illustrates the relationship of the afe input clock and the data into the dac and out of the adc. afe serial interface the afe configuration signals gpio[4], gpio[5], and gpio[6] are used to program the afe internal registers. gpio[4] is the serial clock; gpio[5] is the bidirectional data line for register reprogramming and reading, and when gpio[6] is asserted high, the registers are in write mode. drive these lines low if not used. refer to the max2980 data sheet for more information on the afe serial interface timing. upgrading and programming mac there are wide ranges of boot options that provide good flexibility in running code applications on the max2986 through different chip interfaces. the selec- tion of different boot modes is possible through boot pins and flash type pins, which are sensed during the max2986 startup process. there are two boot modes: 1) downloading encrypted flash-resident code: the image can be downloaded into flash memory using either an i 2 c tm or spi interface. the code image address is stored at the start of flash memory. the encrypted code image in flash can be updated using tftp protocol. 2) simple code downloaded through uart: the max2986 is configurable to accept code image from the uart. the first 4 bytes of the image specify the memory location in ssram to which the binary image should be copied (0x2020000 0x203ffff). the next 4 bytes specify the length of the image (excluding 8 header and 4 tail bytes), in terms of words. the specified length cannot be greater than 128kb (size of ssram) and must be nonzero, other- wise the boot will restart simple code downloaded through the uart after issuing an appropriate error message to the host. the last 4 bytes of image are the checksum. after the image is loaded and checksum is valid, the image is launched by jumping to the target (destination) address, otherwise, the boot restarts sim- ple code downloaded through the uart. five pins are used to determine the boot mode. table 17 shows the corresponding settings (pu: pulled up, pd: pulled down, x: don? care). pullup and pulldown resis- tors are 10k ? . gpio[8] and gpio[10] are two pins that are used for flash operations. these two pins are output in flash operations but they would be input in the sys- tem boot process. if an error occurs during the boot process, the error code is indicated on the led pins: gpio[21] (led0_ bp0), gpio[22] (led1_ bp1), and gpio[23] (led2_bp2) purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. spi is a trademark of motorola, inc.
max2986 integrated powerline digital transceiver 22 ______________________________________________________________________________________ according to table 18. pullup/pulldown resistors for leds are 1k ? or less. the states of gpio pins and initialization pins during the boot process are shown in table 17. see the pin description for more information. clocks and reset the max2986 has a built-in oscillator that requires an external crystal. use a 30mhz crystal with stability of 25ppm max over operating temperature. all other nec- essary clocks are generated internally by means of two integrated plls. figure 24 illustrates how to connect a crystal to the max2986. if the external clock oscillator is used, leave xout unconnected as shown in figure 25. since the reset signal reset is used in pll modules, it must be activated after the pll clock generation delay, which is about 0.5ms. gpio pin usage the max2986 firmware makes special use of gpio pins as described in table 19. gpio pins are utilized in input, output, or both directions. table 18. boot error codes led2_bp2 led1_bp1 led0_bp0 boot status 001 the flash does not contain a valid image. 010 the size of the image is more than 128kb. 011 the base address of the image is out of the allowed range. 100 checksum error. 101 no flash is available. 110 invalid boot mode. 111 000 no error. table 17. boot modes boot/ft pins boot mode flash type gpio[23] gpio[22] gpio[21] gpio[8] gpio[10] flash type is spi (at45db) 010pupu flash type is spi (sst25vf) 110pupu encrypted image downloaded from flash flash type is i 2 c x10pdpu code downloaded through uart x000 x pu* x = don? care. * pu: if pin gpio[10] is pulled down instead of pulled up, it indicates that there is no flash device connected to the chip. if t his is the case and if led0_bp0 = led1_bp1 = 0, then the gpio[8] line must be pulled up.
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 23 xin xout r f 1m ? c 1 15pf c 2 15pf crystal 30mhz max2986 figure 24. connecting a crystal to the max2986 xin clock oscillator out 30mhz xout n.c. max2986 figure 25. connecting a clock oscillator to the max2986
max2986 integrated powerline digital transceiver 24 ______________________________________________________________________________________ table 19. gpio pin usage by the max2986 firmware location gpio max2986 ev kit use description c4 gpio[23] hpact_bp2 output: input: drive afe interface activity led boot pin 2 a5 gpio[22] hplink_bp1 output: input: drive afe interface link status led boot pin 1 b6 gpio[21] hpcol_bp0 output: input: drive afe interface collision led boot pin 0 c9 gpio[13] pid2 output: input: none processor id, bit 2 b9 gpio[12] pid1 output: input: none processor id, bit 1 a9 gpio[11] pid0 output: input: none processor id, bit 0 b10 gpio[10] iwcs_ft1 output: input: flash interface chip select nonvolatile memory bit 1 a10 gpio[9] isdat output: input: flash interface data (write) flash interface data (read) b11 gpio[8] iscl_ft0 output: input: flash interface serial clock nonvolatile memory, bit 0 a11 gpio[7] pdafe output: input: afe power-down none b12 gpio[6] awr_ul1 output: input: afe serial interface write upper interface select, bit 1 a12 gpio[5] asdat output: input: afe serial interface data (write) afe serial interface data (read) a13 gpio[4] ascl_ul0 output: input: afe serial interface clock upper layer interface select, bit 0 b4 gpio[3] ul2 output: input: none upper layer interface select, bit 2 a4 gpio[2] output: input: it is used to control external usb circuit none
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 25 powerline 802.3 ethernet mac mii controller 4-bit rx ethernet connector hpf mac dsp max2980 afe dac lpf/agc adc line drive control 4-bit tx signaling 10-bit data bus signaling control serial bus max2986 phy/mac figure 26. powerline baseband to mii application block diagram usb 1.1 usb connector hpf mac max2980 afe dac lpf/agc adc line drive control 10-bit data bus signaling control serial bus max2986 phy/mac dsp figure 27. powerline baseband to usb application block diagram fifo controller signaling control fifo 8-bit data bus hpf mac max2980 afe dac lpf/agc adc line drive control 10-bit data bus signaling control serial bus max2986 phy/mac dsp figure 28. powerline baseband to fifo application block diagram
max2986 integrated powerline digital transceiver 26 ______________________________________________________________________________________ powerline ethernet phy max2986 phy/mac embedded 802.3 ethernet mac 4-bit rx ethernet connector hpf homeplug mac max2980 afe dac lpf/agc adc line drive control 4-bit tx signaling 10-bit data bus signaling control serial bus dsp t ypical application circuit chip information process: cmos
max2986 integrated powerline digital transceiver ______________________________________________________________________________________ 27 a b c d e f g h j k l m n a b c d e f g h j k l m n 12345678910111213 12345678910111213 dv dd dv ss av dd gpio[2] gpio[22] v dd33 gpio[17] gpio[14] gpio[11] gpio[9] gpio[7] gpio[5] gpio[4] dgnd av ss gpio[0] gpio[3] usbd+ gpio[21] gpio[18] gpio[15] gpio[12] gpio[10] gpio[8] gpio[6] n.c. v dd33 dgnd gpio[1] gpio[23] usbd- gpio[20] gpio[19] gpio[16] gpio[13] v dd18 jtms jtdi v dd33 n.c. dgnd dgnd dgnd dgnd dgnd dgnd v dd18 n.c. n.c. n.c. n.c. jrtclk dgnd afefrz v dd18 dgnd dgnd dgnd afetxen xin xout dgnd v dd18 miitxen v dd33 dgnd afereset afedad[0] afedadi1] afedad[2] v dd18 jtdo jtck afedad[3] afedad[4] afedad[5] afedad[6] miirxdv v dd33 afedad[7] afedad[8] afedad[9] v dd18 miimdc miidat[7] miidat[5] afeclk aferen afepdrx n.c. dgnd dgnd uarttxd dgnd dgnd v dd18 miicrs miidat[6] miimdio v dd33 dv dd dv ss v dd33 ethrxd[1] uartrxd ethtxd[3] ethtxd[2] ethtxclk v dd33 miirxer miidat[4] miidat[0] av dd av ss ethmdc ethrxclk ethrxd[2] ethrxd[0] ethrxdv ethtxd[0] ethtxen dgnd dgnd n.c. v dd33 dgnd ethcol ethcrs ethmdio ethrxd[3] dgnd ethrxer ethtxd[1] ethtxer miiclk miidat[3] miidat[2] miidat[1] usbreset jtrst bufrd bufwr bufcs reset max2986 csbga pin configuration
max2986 integrated powerline digital transceiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pa c kag e information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 144 ball csbga.eps a 1 1 21-0163 package outline, 144 ball csbga, 12x12x1.4mm, 0.8mm pitch

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